emu: CBW/CWD sign extension operations
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@@ -588,6 +588,8 @@ impl i8088 {
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0x95 => xchg[reg=a, reg=bp] / 3, // XCHG ax, bp
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0x95 => xchg[reg=a, reg=bp] / 3, // XCHG ax, bp
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0x96 => xchg[reg=a, reg=si] / 3, // XCHG ax, si
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0x96 => xchg[reg=a, reg=si] / 3, // XCHG ax, si
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0x97 => xchg[reg=a, reg=di] / 3, // XCHG ax, di
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0x97 => xchg[reg=a, reg=di] / 3, // XCHG ax, di
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0x98 => cbw[reg=a, reglo=a] / 2, // CBW
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0x99 => cwd[reg=d, reg=a] / 5, // CWD
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0x9C => push[bus, regval=ss, reg=sp, flags] / 14, // PUSHF
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0x9C => push[bus, regval=ss, reg=sp, flags] / 14, // PUSHF
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0x9D => pop[bus, regval=ss, reg=sp, flags] / 12, // POPF
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0x9D => pop[bus, regval=ss, reg=sp, flags] / 12, // POPF
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// 0x9E SAHF not implemented
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// 0x9E SAHF not implemented
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@@ -6,7 +6,7 @@ use emu::num_traits::CheckedShr;
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use emu::dos;
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use emu::dos;
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use emu::flags::{FlagOp, Flags};
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use emu::flags::{FlagOp, Flags};
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use emu::i8088::{RepPrefix, i8088};
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use emu::i8088::{RepPrefix, i8088};
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use emu::operands::{Address, DynLValue, FarPtr, LValue, Operand, Reg, RValue};
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use emu::operands::{Address, DynLValue, FarPtr, LValue, Operand, Reg, RegLo, RValue};
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use emu::pc::Bus;
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use emu::pc::Bus;
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macro_rules! string_op {
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macro_rules! string_op {
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@@ -101,6 +101,10 @@ pub fn call(mut ip: Reg, bus: &mut Bus, ss: u16, sp: Reg, rel16: u16) {
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ip.write(target);
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ip.write(target);
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}
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}
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pub fn cbw(mut ax: Reg, al: RegLo) {
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ax.write(al.read() as i8 as u16);
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}
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pub fn clc(flags: &mut Flags) {
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pub fn clc(flags: &mut Flags) {
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flags.update(FlagOp::Eager { cf: false,
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flags.update(FlagOp::Eager { cf: false,
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pf: flags.pf(),
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pf: flags.pf(),
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@@ -152,6 +156,10 @@ where T: Operand + RValue<T>,
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});
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});
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}
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}
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pub fn cwd(mut dx: Reg, ax: Reg) {
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dx.write(if ax.read() < 0x8000 { 0x0000 } else { 0xFFFF });
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}
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pub fn dec<T: Operand, LVal: LValue<T>>(flags: &mut Flags, mut dst: LVal) {
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pub fn dec<T: Operand, LVal: LValue<T>>(flags: &mut Flags, mut dst: LVal) {
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let dst_before = dst.read();
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let dst_before = dst.read();
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let res = dst_before.wrapping_sub(&T::one());
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let res = dst_before.wrapping_sub(&T::one());
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