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emu: use mask, not mod for ROL/ROR CF calc. No flags when SHL/SHR=0

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This commit is contained in:
Jared Burce
2021-03-30 23:27:55 -07:00
parent a789b7e87d
commit a4e5d03e22
3 changed files with 13 additions and 9 deletions
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12
src/emu/flags.rs
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@@ -38,8 +38,12 @@ impl Flags {
FlagOp::Eager => { self.res & 1 << CF_BIT != 0 },
FlagOp::DEC { cf } => { cf },
FlagOp::INC { cf } => { cf },
FlagOp::ROL { dst, src, bits, .. } => { dst & (self.sign_mask >> ((src - 1) % bits as u16)) != 0 },
FlagOp::ROR { dst, src, bits, .. } => { dst & (1 << ((src - 1) % bits as u16)) != 0 },
FlagOp::ROL { dst, src, rot_mask, .. } => {
dst & (self.sign_mask >> ((src.wrapping_sub(1)) & rot_mask as u16)) != 0
},
FlagOp::ROR { dst, src, rot_mask, .. } => {
dst & (1 << ((src.wrapping_sub(1)) & rot_mask as u16)) != 0
},
FlagOp::SAR { dst, src, sign_bit } => {
match 1u16.checked_shl(src as u32 - 1) {
Some(carrymask) => dst & carrymask != 0,
@@ -126,8 +130,8 @@ pub enum FlagOp {
Eager, // precomputed into result, for e.g. POPF
DEC { cf: bool },
INC { cf: bool },
ROL { dst: u16, src: u16, bits: u8, cf: bool, pf: bool, af: bool, zf: bool, sf: bool },
ROR { dst: u16, src: u16, bits: u8, cf: bool, pf: bool, af: bool, zf: bool, sf: bool },
ROL { dst: u16, src: u16, rot_mask: u16, cf: bool, pf: bool, af: bool, zf: bool, sf: bool },
ROR { dst: u16, src: u16, rot_mask: u16, cf: bool, pf: bool, af: bool, zf: bool, sf: bool },
SAR { dst: u16, src: u16, sign_bit: bool },
SHL { dst: u16, src: u16 },
SHR { dst: u16, src: u16 },