535 lines
16 KiB
Rust
535 lines
16 KiB
Rust
use std::cell::Cell;
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use std::fmt::{Debug, Formatter};
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use super::byteorder::{ByteOrder, LittleEndian};
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use emu::pc::Bus;
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#[allow(non_camel_case_types)]
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#[derive(Clone, Debug, Default)]
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pub struct i8088 {
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// Data Registers
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pub a: Cell<u16>,
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pub b: Cell<u16>,
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pub c: Cell<u16>,
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pub d: Cell<u16>,
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// Index Registers
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pub si: Cell<u16>, // Source Index
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pub di: Cell<u16>, // Dest Index
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pub bp: Cell<u16>, // Base Pointer
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pub sp: Cell<u16>, // Stack Pointer
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// Segment Registers
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pub cs: Cell<u16>, // Code Segment
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pub ds: Cell<u16>, // Data Segment
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pub es: Cell<u16>, // Extra Segment
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pub ss: Cell<u16>, // Stack Segment
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// Pointer Register
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pub ip: Cell<u16>,
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// Status Register
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pub flags: Flags,
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}
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#[derive(Clone, Copy, Default)]
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pub struct Flags {
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cf: bool, // 0: Carry Flag: 1=CY(Carry), 0=NC(No Carry)
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// 1: Reserved
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pf: bool, // 2: Parity Flag: 1=PE(Even), 0=PO(Odd)
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// 3: Reserved
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af: bool, // 4: Adjust Flag: 1=AC(Aux Carry), 0=NA(No Aux Carry)
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// 5: Reserved
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zf: bool, // 6: Zero Flag: 1=ZR(Zero), 0=NZ(Not Zero)
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sf: bool, // 7: Sign Flag: 1=NG(Negative), 0=PL(Positive)
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tf: bool, // 8: Trap Flag
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ie: bool, // 9: (Real name "IF") Interrupt Enable: 1=EI(Enable Interrupt), 0=DI(Disable Interrupt)
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df: bool, // 10: Direction Flag: 1=DN(Down), 0=UP(Up)
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of: bool, // 11: Overflow Flag: 1=OV(Overflow), 0=NV(Not Overflow)
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// bits 12-15 always 1
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}
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mod ops {
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use emu::byteorder::{ByteOrder, LittleEndian};
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use emu::dos;
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use emu::i8088::{Address, Bus, LValue, Reg, RValue, i8088, segoff_to_addr};
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pub fn show(cpu: &mut i8088) {
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println!("{:#X?}", cpu);
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}
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pub fn peek(addr: &(impl Address + RValue<u8>)) {
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println!("PEEK: @{:#X} = {:#X} ({})", addr.addr(), addr.read(), addr.read());
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}
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pub fn call(ip: &mut Reg, ss: u16, sp: &mut Reg, mem: &mut [u8], addr: i16) {
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let target = ip.read().wrapping_add(addr as u16);
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push16(ss, sp, mem, ip.read());
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ip.write(target);
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}
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pub fn int(cpu: &mut i8088, bus: &mut Bus, num: &u8) {
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match num {
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0x21 => dos::interrupt(cpu, bus),
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_ => unimplemented!("interrupt: {:02X}\ncpu: {:#X?}", num, cpu)
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}
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}
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pub fn mov<T>(dst: &mut impl LValue<T>, src: &impl RValue<T>) {
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dst.write(src.read());
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}
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pub fn nop() {}
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pub fn pop16(ss: u16, sp: &mut Reg, mem: &[u8]) -> u16 {
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let val = LittleEndian::read_u16(&mem[segoff_to_addr(ss.read(), sp.read())..]);
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sp.write(sp.read() + 2);
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val
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}
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pub fn push16(ss: u16, sp: &mut Reg, mem: &mut [u8], val: u16) {
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// XXX: Not checking for stack faults or anything
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sp.write(sp.read() - 2);
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LittleEndian::write_u16(&mut mem[segoff_to_addr(ss.read(), sp.read())..], val);
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}
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pub fn ret(ip: &mut Reg, ss: u16, sp: &mut Reg, mem: &[u8]) {
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ip.write(pop16(ss, sp, mem));
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}
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}
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pub trait LValue<T> {
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fn write(&mut self, val: T);
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}
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pub trait RValue<T> {
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fn read(&self) -> T;
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}
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pub trait Address {
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fn addr(&self) -> usize;
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}
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impl RValue<u8> for u8 {
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fn read(&self) -> u8 {
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*self
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}
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}
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impl LValue<u16> for u16 {
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fn write(&mut self, val: u16) {
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*self = val;
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}
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}
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impl RValue<u16> for u16 {
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fn read(&self) -> u16 {
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*self
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}
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}
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pub struct Reg<'a> {
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reg: &'a Cell<u16>
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}
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impl LValue<u16> for Reg<'_> {
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fn write(&mut self, val: u16) {
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self.reg.set(val);
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}
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}
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impl RValue<u16> for Reg<'_> {
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fn read(&self) -> u16 {
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self.reg.get()
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}
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}
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struct RegHi<'a> {
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reg: &'a Cell<u16>
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}
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impl LValue<u8> for RegHi<'_> {
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fn write(&mut self, val: u8) {
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write_hi(&mut self.reg, val);
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}
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}
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impl RValue<u8> for RegHi<'_> {
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fn read(&self) -> u8 {
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read_hi(self.reg)
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}
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}
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struct Addr<'a> {
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bus: &'a mut Bus,
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addr: usize
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}
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impl Address for Addr<'_> {
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fn addr(&self) -> usize {
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self.addr
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}
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}
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impl LValue<u8> for Addr<'_> {
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fn write(&mut self, val: u8) {
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self.bus.write(self.addr, val);
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}
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}
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impl RValue<u8> for Addr<'_> {
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fn read(&self) -> u8 {
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self.bus.read(self.addr)
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}
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}
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struct RegLo<'a> {
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reg: &'a Cell<u16>
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}
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impl LValue<u8> for RegLo<'_> {
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fn write(&mut self, val: u8) {
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write_lo(&mut self.reg, val);
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}
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}
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impl RValue<u8> for RegLo<'_> {
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fn read(&self) -> u8 {
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read_lo(self.reg)
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}
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}
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macro_rules! step {
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// Base case: all args processed and ready to call op
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(@code ( $($done:tt)* ),
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$cpu:expr, $bus:expr, $prefix:tt, $modrm:tt, $name:ident, $cycles:literal,
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()) => {
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ops::$name($($done),*);
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};
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// Inductive case: decode next arg to be placed in list
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(@code ( $($done:tt)* ),
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$cpu:expr, $bus:expr, $prefix:tt, $modrm:tt, $name:ident, $cycles:literal,
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($next:ident $(= $nextrhs:ident)? $($rest:ident $(= $restrhs:ident)?)*)) => {
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step!(@$next$(= $nextrhs)?
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// "cookie" tt to be passed thru to @arg so we have all the args for the recursive step
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( ($($done)*), $cpu, $bus, $prefix, $modrm, $name, $cycles, ($($rest $(= $restrhs)?)*) ),
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$cpu, $bus, $prefix, $modrm)
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};
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// accept an argument from a decoder and recur to look for next arg
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(@arg ( ($($done:tt)*), $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt,
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$name:ident, $cycles:literal, $rest:tt )
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$(, $arg:expr)?) => {
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step!(@code ($($done)* $($arg)?), $cpu, $bus, $prefix, $modrm, $name, $cycles, $rest)
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};
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// decoder deferring to sub-decoders, push them onto the decoder stack to process next
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(@push ( $done:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt, $name:ident, $cycles:literal, ( $($rest:tt)* ) ),
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( $($args:tt)* )) => {
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step!(@code $done, $cpu, $bus, $prefix, $modrm, $name, $cycles, ( $($args)* $($rest)* ))
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};
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// Argument Decoders
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(@addr $cookie:tt, $cpu:expr, $bus:expr, ($segment:ident, $prefix_loop:lifetime), $modrm:tt) => { {
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let a16 = i8088::next_ip16($cpu.cs.get(), &mut $cpu.ip, $bus);
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let addr = segoff_to_addr($segment.unwrap(), a16);
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step!(@arg $cookie, &mut Addr { bus: $bus, addr: addr } )
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} };
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(@bus $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, $bus)
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};
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(@cpu $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, $cpu)
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};
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(@d8 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => { {
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let d8 = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus);
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step!(@arg $cookie, &d8)
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} };
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(@d16 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => { {
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let d16 = i8088::next_ip16($cpu.cs.get(), &mut $cpu.ip, $bus);
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step!(@arg $cookie, &d16)
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} };
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(@mem $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, &mut $bus.ram)
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};
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(@modrm16 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt,
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($modrm_val:ident, { $($val:literal => $($args:ident = $argrhs:tt),*),*$(,)? }, $modrm8:tt)) => { {
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let modrm_val = $modrm_val & !0x38;
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match modrm_val {
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$( $val => step!(@push $cookie, ($($args = $argrhs)* ) ) ),*,
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_ => unimplemented!("modrm: {:02X}({:02X})\ncpu: {:#X?}", $modrm_val, modrm_val, $cpu)
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}
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} };
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(@prefix $cookie:tt, $cpu:expr, $bus:expr, ($segment:ident, $prefix_loop:lifetime), $modrm:tt) => { continue $prefix_loop; };
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(@r16 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, ($modrm:ident, $modrm16:tt, $modrm8:tt)) => {
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// TODO: Should these also be passed into the macro like the modrm specs?
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match $modrm >> 3 & 0x7 {
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0 => step!(@arg $cookie, &mut Reg { reg: &$cpu.a } ),
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1 => step!(@arg $cookie, &mut Reg { reg: &$cpu.c } ),
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2 => step!(@arg $cookie, &mut Reg { reg: &$cpu.d } ),
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3 => step!(@arg $cookie, &mut Reg { reg: &$cpu.b } ),
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4 => step!(@arg $cookie, &mut Reg { reg: &$cpu.sp } ),
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5 => step!(@arg $cookie, &mut Reg { reg: &$cpu.bp } ),
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6 => step!(@arg $cookie, &mut Reg { reg: &$cpu.si } ),
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7 => step!(@arg $cookie, &mut Reg { reg: &$cpu.di } ),
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_ => unreachable!()
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};
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};
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(@r8 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, ($modrm:ident, $modrm16:tt, $modrm8:tt)) => {
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// TODO: Should these also be passed into the macro like the modrm specs?
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match $modrm >> 3 & 0x7 {
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0 => step!(@arg $cookie, &mut RegHi { reg: &$cpu.a } ),
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1 => step!(@arg $cookie, &mut RegHi { reg: &$cpu.c } ),
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2 => step!(@arg $cookie, &mut RegHi { reg: &$cpu.d } ),
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3 => step!(@arg $cookie, &mut RegHi { reg: &$cpu.b } ),
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4 => step!(@arg $cookie, &mut RegLo { reg: &$cpu.a } ),
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5 => step!(@arg $cookie, &mut RegLo { reg: &$cpu.c } ),
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6 => step!(@arg $cookie, &mut RegLo { reg: &$cpu.d } ),
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7 => step!(@arg $cookie, &mut RegLo { reg: &$cpu.b } ),
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_ => unreachable!()
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};
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};
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(@reg=$reg:ident $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, &mut Reg { reg: &$cpu.$reg });
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};
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(@reghi=$reg:ident $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, &mut RegHi { reg: &$cpu.$reg });
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};
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(@reglo=$reg:ident $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, &mut RegLo { reg: &$cpu.$reg });
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};
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(@regval=$reg:ident $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => {
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step!(@arg $cookie, $cpu.$reg.get());
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};
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(@rel16 $cookie:tt, $cpu:expr, $bus:expr, $prefix:tt, $modrm:tt) => { {
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let mut buf = [0; 2];
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buf[0] = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus);
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buf[1] = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus);
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step!(@arg $cookie, LittleEndian::read_i16(&buf))
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} };
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(@seg=$seg:ident $cookie:tt, $cpu:expr, $bus:expr, ($segment:ident, $prefix_loop:lifetime), $modrm:tt) => { {
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$segment = $segment.or(Some($cpu.$seg.get()));
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step!(@arg $cookie)
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} };
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// Group Decoder
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(@group $cpu:expr, $bus:expr, $prefix:tt, ($modrm:ident, $modrm16:tt, $modrm8:tt), $code:literal,
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{ $( $subcode:literal =>
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$name:ident[$($args:ident $(= $argrhs:ident)?),*] / $cycles:literal),*$(,)? } ) => { {
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let subcode = $modrm & 0x38;
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match subcode {
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$( $subcode => step!(@code (), $cpu, $bus, $prefix, ($modrm, $modrm16, $modrm8), $name, $cycles, ($($args $(= $argrhs)?)*)) ),*,
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_ => unimplemented!("opcode: {:02X} {:02X}({:02X})\ncpu: {:#X?}", $code, $modrm, subcode, $cpu)
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} }
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};
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// Entry Point
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(($cpu:expr, $bus:expr) =>
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opcodes: { $(
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$code:literal
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// Non-group opcodes
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$( $($ext:pat)? =>
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$name:ident[$($args:ident $(= $argrhs:ident)?),*] / $cycles:literal
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)?
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// Group opcodes
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$( : $subcodes:tt )?
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),*
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$(,)? },
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modrm16: $modrm16:tt,
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modrm8: $modrm8:tt
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) => {
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{
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let mut segment = None;
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let modrm: u8; // Type ascription unnecessary but gives better err messages when missing $ext
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'prefix_loop: loop {
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let opcode = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus);
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match(opcode) {
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$( $( $code => {
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$( let $ext = (); /* No-op just to trigger expansion. */
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modrm = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus); )?
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step!(@code (), $cpu, $bus, (segment, 'prefix_loop), (modrm, $modrm16, $modrm8), $name, $cycles, ($($args $(= $argrhs)?)*))
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}
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)?
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$( $code => {
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modrm = i8088::next_ip($cpu.cs.get(), &mut $cpu.ip, $bus);
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step!(@group $cpu, $bus, (segment, 'prefix_loop), (modrm, $modrm16, $modrm8), $code, $subcodes)
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}
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)?
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),*,
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_ => unimplemented!("opcode: {:02X}\ncpu: {:#X?}", opcode, $cpu)
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}
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// Only prefixes loop and they do so with an explicit continue statement
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break;
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}
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}
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}
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}
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pub const fn segoff_to_addr(segment: u16, offset: u16) -> usize {
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let segaddr = (segment as usize) << 4;
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segaddr + offset as usize
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}
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pub fn read_hi(val: &Cell<u16>) -> u8 {
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let mut buf = [0; 2];
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LittleEndian::write_u16(&mut buf, val.get());
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buf[1] as u8
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}
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pub fn read_lo(val: &Cell<u16>) -> u8 {
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let mut buf = [0; 2];
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LittleEndian::write_u16(&mut buf, val.get());
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buf[0] as u8
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}
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pub fn write_hi(reg: &Cell<u16>, val: u8) {
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let mut buf = [0; 2];
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LittleEndian::write_u16(&mut buf, reg.get());
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buf[1] = val;
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reg.set(LittleEndian::read_u16(&buf))
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}
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pub fn write_lo(reg: &Cell<u16>, val: u8) {
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let mut buf = [0; 2];
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LittleEndian::write_u16(&mut buf, reg.get());
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buf[1] = val;
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reg.set(LittleEndian::read_u16(&buf));
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}
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impl i8088 {
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pub fn run(&mut self, bus: &mut Bus) {
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loop {
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step!((self, bus) =>
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opcodes: {
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0x26 => nop[seg=es, prefix] / 2,
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0x2e => nop[seg=cs, prefix] / 2,
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0x36 => nop[seg=ss, prefix] / 2,
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0x3e => nop[seg=ds, prefix] / 2,
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0x60 => show[cpu] / 0, // Fake opcode for debugging
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0x61 => peek[seg=ds, addr] / 0, // Fake opcode for debugging
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0x8B _ => mov[r16, modrm16] / "2/12+",
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0x8C: { 0x08 => mov[modrm16, reg=cs] / "2/13+", },
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0x8E: { 0x18 => mov[reg=ds, modrm16] / "2/12+", },
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0x90 => nop[] / 3,
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0xB4 => mov[reghi=a, d8] / 4,
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0xBA => mov[reg=d, d16] / 4,
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0xC3 => ret[reg=ip, regval=ss, reg=sp, mem] / 20,
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0xCD => int[cpu, bus, d8] / 71,
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0xE8 => call[reg=ip, regval=ss, reg=sp, mem, rel16] / 23,
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},
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modrm16: {
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0xC0 => reg=a,
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0xC1 => reg=c,
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0xC2 => reg=d,
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0xC3 => reg=b,
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0xC4 => reg=sp,
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0xC5 => reg=bp,
|
|
0xC6 => reg=si,
|
|
0xC7 => reg=di,
|
|
},
|
|
modrm8: {
|
|
0xC0 => reglo=a,
|
|
0xC1 => reglo=c,
|
|
0xC2 => reglo=d,
|
|
0xC3 => reglo=b,
|
|
0xC4 => reghi=a,
|
|
0xC5 => reghi=c,
|
|
0xC6 => reghi=d,
|
|
0xC7 => reghi=b,
|
|
})
|
|
}
|
|
}
|
|
|
|
fn next_ip<'a>(cs: u16, ip: &mut Cell<u16>, bus: &Bus) -> u8 {
|
|
let eip = segoff_to_addr(cs, ip.get());
|
|
ip.set(ip.get() + 1);
|
|
|
|
// We'll assume cpu is always executing in RAM. Also assume the
|
|
// IP doesn't reach the end of the segment (My guess is that it
|
|
// should loop within the segment if it did)
|
|
bus.ram[eip - Bus::RAM_LOCATION]
|
|
}
|
|
|
|
fn next_ip16<'a>(cs: u16, ip: &mut Cell<u16>, bus: &Bus) -> u16 {
|
|
let eip = segoff_to_addr(cs, ip.get());
|
|
ip.set(ip.get() + 2);
|
|
|
|
// We'll assume cpu is always executing in RAM. Also assume the
|
|
// IP doesn't reach the end of the segment (My guess is that it
|
|
// should loop within the segment if it did)
|
|
let buf = &bus.ram[eip - Bus::RAM_LOCATION .. eip + 2 - Bus::RAM_LOCATION];
|
|
LittleEndian::read_u16(buf)
|
|
}
|
|
}
|
|
|
|
|
|
impl From<u16> for Flags {
|
|
fn from(flags: u16) -> Self {
|
|
Self {
|
|
cf: flags & 1 != 0,
|
|
pf: flags & 1 << 2 != 0,
|
|
af: flags & 1 << 4 != 0,
|
|
zf: flags & 1 << 6 != 0,
|
|
sf: flags & 1 << 7 != 0,
|
|
tf: flags & 1 << 8 != 0,
|
|
ie: flags & 1 << 9 != 0,
|
|
df: flags & 1 << 10 != 0,
|
|
of: flags & 1 << 11 != 0,
|
|
}
|
|
}
|
|
}
|
|
|
|
impl From<Flags> for u16 {
|
|
fn from(flags: Flags) -> Self {
|
|
0b1111_0000_0010_1010 // Not sure what all reserved bits should be, but it shouldn't matter
|
|
| (flags.cf as u16)
|
|
| (flags.pf as u16) << 2
|
|
| (flags.af as u16) << 4
|
|
| (flags.zf as u16) << 6
|
|
| (flags.sf as u16) << 7
|
|
| (flags.tf as u16) << 8
|
|
| (flags.ie as u16) << 9
|
|
| (flags.df as u16) << 10
|
|
| (flags.of as u16) << 11
|
|
}
|
|
}
|
|
|
|
impl Debug for Flags {
|
|
fn fmt(&self, fmt: &mut Formatter) -> Result<(), std::fmt::Error> {
|
|
use std::fmt::Write;
|
|
fmt.write_str("[ ")?;
|
|
for flag in [ (self.cf, "CF "),
|
|
(self.pf, "PF "),
|
|
(self.af, "AF "),
|
|
(self.zf, "ZF "),
|
|
(self.sf, "SF "),
|
|
(self.tf, "TF "),
|
|
(self.ie, "IF "),
|
|
(self.df, "DF "),
|
|
(self.of, "OF ") ].iter() {
|
|
if flag.0 { fmt.write_str(flag.1)? };
|
|
}
|
|
fmt.write_char(']')?;
|
|
Ok(())
|
|
}
|
|
}
|