04348a816e
emu: Fake opcode ASSERT for testing
2021-03-12 22:19:45 -08:00
0c55ff9b36
emu: modrm displacement, LEA instruction
2021-03-12 08:01:28 -08:00
adb7e672d9
emu: accept cycle cost for modrm spec (and ignore for now)
2021-03-12 04:10:15 -08:00
c372a96b7c
emu: all MOV opcodes (no modrm base/index/displacement modes yet)
2021-03-12 04:02:27 -08:00
ac7b3b16a1
emu: factor out utils into own module
2021-03-12 02:27:00 -08:00
27bc36f9d2
emu: factor out operations and operands into own module
2021-03-11 22:55:51 -08:00
b950a56d26
emu: segment prefix, addr Arg decoder, Addr arg trait, NOP opcode
2021-03-11 05:55:07 -08:00
71bcec1574
emu: wrap cpu regs in Cell. r16 addr mode.
...
r16 + modrm16 allowed cpu regs to alias. Wrap them in Cell to allow
this. We also create a Reg wrapper when passing regs so that we can
pass as &mut while simultaneously having other references to the same
reg.
2021-03-10 07:16:08 -08:00
49789c74f9
emu: show/peek debug instructions
2021-03-09 06:42:12 -08:00
20bfc45dae
emu: modrm16 arg decoder
2021-03-08 06:20:20 -08:00
3f2c12a83c
emu: machinery for ModRM propegation
2021-03-08 06:17:45 -08:00
e1a6feb6f5
emu: Factor out hi/lo register access
2021-03-06 23:47:56 -08:00
1e32036bf7
emu: INT instruction, standalone dos function for now
2021-03-06 05:26:40 -08:00
0f4e52697a
emu: reghi & d8 address modes. make next_ip assoc instead of member
...
next_ip would borrow all of the cpu, now we just need IP and CS.
2021-03-06 04:52:09 -08:00
b2aa3fd0e0
emu: MOV generic. Drop Reg16 register wrapper type
2021-03-06 04:18:48 -08:00
be7e926842
emu: dump register file on unimplemented opcode
2021-03-06 02:10:25 -08:00
fa49d19ae0
emu: arg=rhs parsing. d16, reg, regval argtypes. non-generic MOV.
2021-03-06 01:09:17 -08:00
5c39f3b5af
emu ops can get multiple args, mem no longer implicit, implement RET
2021-03-06 01:09:07 -08:00
639e05edac
basic emu skeleton and loop, CALL instruction & rel16 addr mode
2021-03-06 01:08:19 -08:00
